CSCI E-92: Application Note 13

ARM Core Registers
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The ARM v7-M Architecture Reference Manual, Errata markup in section
A2.3.1 "ARM core registers" on page A2-46 has an overview of the
thirteen general-purpose 32-bit registers, R0-R12, and the additional
three special 32-bit registers.  Also, the Application Program Status
Register, or APSR, is used to store various status flags.

In addition to registers R0 through R12, there are also the SP, LR,
and PC.

The SP, or Stack Pointer, is also known as R13.  The Stack Pointer is
used as a pointer to the active stack.  The SP is preset to point to
the top of the Main stack on reset.  An ARMv7-M processor implements
two stacks:

o The Main stack, SP_main or MSP
o The Process stack, SP_process or PSP.

The stack pointer, SP, accesses either SP_main or SP_process, as
appropriate.  The current stack depends on the mode and, in Thread
mode, the value of the CONTROL.SPSEL bit, see "The special-purpose
CONTROL register" on page B1-628.  Processor reset selects and
initializes SP_main, see "Reset behavior" on page B1-641.

The stack grows toward lower addresses.  In a push operation, the SP
is decremented first and then the data to be pushed is written to
memory at the SP address.  This implies that the Top Of Stack (TOS)
data is always pointed to by the SP.  In a pop operation, data is
first read from TOS and then the SP is incremented.

The LR, or Link Register, is also known as R14.  The Link Register is
used to store the Return Link.  This is a value that may be used as
the return address from a subroutine that is entered using a Branch
with Link instruction.  Processor reset sets this register to
0xFFFFFFFF.  The reset value causes a fault condition if the processor
uses it when attempting a subroutine return.  The LR is also updated
on exception entry, see Exception entry behavior on page B1-643.

The PC, or Program Counter, is also known as R15.  The PC is loaded
with the reset handler start address on reset.

The Application Program Status Register (APSR) contains bit fields
that store the state of application events and reserved bits.  The
reserved bits are allocated to system features or are available for
future expansion.  Further information on currently allocated reserved
bits is available in "The special-purpose program status registers,
xPSR" on page B1-624.  Application level software must ignore values
read from reserved bits, and preserve their value on a write.  The
bits are defined as UNK/SBZP.

The fields are:
  N, bit [31]
  Negative condition code flag.  Set to bit [31] of the result of the
  instruction.  If the result is regarded as a two's complement signed
  integer, then N == 1 if the result is negative and N == 0 if it is
  positive or zero.

  Z, bit [30]
  Zero condition code flag.  Set to 1 if the result of the instruction
  is zero, and to 0 otherwise.  A result of zero often indicates an
  equal result from a comparison.

  C, bit [29]
  Carry condition code flag.  Set to 1 if the instruction results in a
  carry condition, for example an unsigned overflow on an addition.

  V, bit [28]
  Overflow condition code flag.  Set to 1 if the instruction results
  in an overflow condition, for example a signed overflow on an
  addition.

  Q, bit [27]
  Set to 1 if a SSAT or USAT instruction changes the input value for
  the signed or unsigned range of the result.  In a processor that
  implements the DSP extension, the processor sets this bit to 1 to
  indicate an overflow on some multiplies.  Setting this bit to 1 is
  called saturation.

  GE[3:0], bits[19:16], DSP extension only
  Greater than or Equal flags.  SIMD instructions update these flags
  to indicate the results from individual bytes or halfwords of the
  operation.  Software can use these flags to control a later SEL
  instruction.  For more information, see SEL on page A7-425.  In a
  processor that does not implement the DSP extension these bits are
  reserved.